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complete quad, 16-bit, high accuracy, serial input, bipolar voltage output dac data sheet ad5764 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2011 analog devices, inc. all rights reserved. features complete quad, 16-bit digital-to-analog converter (dac) programmable output range 10 v, 10.2564 v, or 10.5263 v 1 lsb maximum inl error, 1 lsb maximum dnl error low noise: 60 nv/hz settling time: 10 s maximum integrated reference buffers output control during power-up/brownout programmable short-circuit protection simultaneous updating via ldac asynchronous clr to zero code digital offset and gain adjust logic output control pins dsp-/microcontroller-compatible serial interface temperature range: ?40c to +85c i cmos process technology 1 applications industrial automation open-loop/closed-loop servo control process control data acquisition systems automatic test equipment automotive test and measurement high accuracy instrumentation general description the ad5764 is a quad, 16-bit, serial input, bipolar voltage output dac that operates from supply voltages of 11.4 v to 16.5 v. nominal full-scale output range is 10 v. the ad5764 provides integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry. the part also features a digital i/o port that is programmed via the serial interface. the part incorporates digital offset and gain adjust registers per channel. the ad5764 is a high performance converter that offers guar- anteed monotonicity, integral nonlinearity (inl) of 1 lsb, low noise, and 10 s settling time. during power-up (when the supply voltages are changing), voutx is clamped to 0 v via a low impedance path. the ad5764 uses a serial interface that operates at clock rates of up to 30 mhz and is compatible with dsp and microcontroller interface standards. double buffering allows the simultaneous updating of all dacs. the input coding is programmable to either twos complement or offset binary formats. the asynchro- nous clear function clears the data register to either bipolar zero or zero scale depending on the coding used. the ad5764 is ideal for both closed-loop servo control and open-loop control appli- cations. the ad5764 is available in a 32-lead tqfp, and offers guaranteed specifications over the ?40c to +85c industrial temperature range. see figure 1 for the functional block diagram. table 1. related devices part no. description ad5764r ad5764 with internal voltage reference ad5744r complete quad, 14-bit, high accuracy, serial input, bipolar voltage output dac with internal voltage reference 1 for analog systems designers within industrial/instrumentation equipment oems who need high performance ics at higher voltage levels, i cmos? is a technology platform that enables the development of analog ics capable of 30 v and operating at 15 v supplies, allowing dramatic reductio ns in power consumption and package size, and increased ac and dc performance.
ad5764 data sheet rev. f | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications..................................................................................... 4 ac performance characteristics ................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings............................................................ 9 esd caution.................................................................................. 9 pin configuration and function descriptions........................... 10 typical performance characteristics ........................................... 12 terminology .................................................................................... 17 theory of operation ...................................................................... 18 dac architecture....................................................................... 18 reference buffers........................................................................ 18 serial interface ............................................................................ 18 simultaneous updating via ldac ........................................... 19 transfer function ....................................................................... 20 asynchronous clear ( clr )....................................................... 20 function register ....................................................................... 21 data register............................................................................... 21 coarse gain register ................................................................. 21 fine gain register...................................................................... 22 offset register ............................................................................ 22 offset and gain adjustment worked example...................... 23 design features............................................................................... 24 analog output control ............................................................. 24 digital offset and gain control............................................... 24 programmable short-circuit protection ................................ 24 digital i/o port........................................................................... 24 local ground offset adjust...................................................... 24 applications information .............................................................. 25 typical operating circuit ......................................................... 25 layout guidelines........................................................................... 27 galvanically isolated interface ................................................. 27 microprocessor interfacing....................................................... 27 evaluation board ........................................................................ 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 9/11rev. e to rev. f changed 30 mhz to 50 mhz throughout.................................... 1 changes to t 1 , t 2 , and t 3 parameters, table 4.................................. 6 7/11rev. d to rev. e changed 30 mhz to 50 mhz throughout.................................... 1 changes to t 1 , t 2 , and t 3 parameters, table 4.................................. 6 8/09rev. c to rev. d changes to table 2 and table 3 endnotes ..................................... 6 changes to t 6 parameter and endnotes, table 4 ........................... 7 1/09rev. b to rev. c changes to general description section ...................................... 1 changes to figure 1.......................................................................... 3 changes to table 2 conditions ....................................................... 4 changes to table 3 conditions ....................................................... 5 changes to table 4 conditions ....................................................... 6 changes to figure 5.......................................................................... 8 changes to table 5............................................................................ 9 changes to table 6.......................................................................... 10 changes to figure 34...................................................................... 19 changes to table 7 and table 10................................................... 20 added table 8; renumbered sequentially .................................. 20 changes to table 11 and table 12 ................................................ 21 changes to digital offset and gain control section ................ 24 changes to table 20 ....................................................................... 26 deleted ad5764 to mc68hc11 interface section.................... 27 deleted figure 38; renumbered sequentially ............................ 27 deleted ad5764 to 8xc51 interface section, figure 39, ad5764 to adsp-2101 interface section, figure 40, and ad5764 to pic16c6x/pic16c7x interface section .................. 28 04/08rev. a to rev. b changes to table summary statement, specifications section...4 changes to power requirements parameter, table 2 and table summary statement................................................................5 changes to t 16 parameter, table 4 ....................................................6 changes to table 6.......................................................................... 10 changed v ss /v dd to av ss /av dd in typical performance characteristics section .................................................................. 13 changes to table 16 ....................................................................... 22 changes to table 18 ....................................................................... 23 changes to typical operating circuit section........................... 28 changes to ad5764 to adsp-2101 section ............................... 29 changes to ordering guide .......................................................... 30 1/07rev. 0 to rev. a changes to absolute maximum ratings..................................... 10 changes to figure 25 and figure 26............................................. 16 3/06revision 0: initial version
data sheet ad5764 rev. f | page 3 of 28 functional block diagram 05303-001 input reg c gain reg c offset reg c data reg c 16 dac c input reg d gain reg d offset reg d data reg d 16 dac d g1 g2 input reg b gain reg b offset reg b data reg b 16 dac b input reg a gain reg a offset reg a data reg a 16 16 dac a ldac refcd rstin rstout refab refgnd agndd voutd agndc voutc agndb voutb agnda vouta iscc reference buffers sdin sclk sync sdo d0 d1 bin/2scomp clr pgnd dv cc dgnd g1 g2 g1 g2 g1 g2 av dd av ss av dd av ss input shift register and control logic voltage monitor and control reference buffers ad5764 figure 1.
ad5764 data sheet rev. f | page 4 of 28 specifications av dd = 11.4 v to 16.5 v, av ss = ?11.4 v to ?16.5 v, agndx = dgnd = refgnd = pgnd = 0 v; refab = refcd = 5 v; dv cc = 2.7 v to 5.25 v, r load = 10 k, c l = 200 pf. temperature range: ?40c to +85c; typical at +25c. device functionality is guaranteed to +105c with degraded performance. all specifications t min to t max , unless otherwise noted. table 2. parameter a grade b grade c grade unit test conditions/comments accuracy outputs unloaded resolution 16 16 16 bits relative accuracy (inl) 4 2 1 lsb max differential nonlinearity 1 1 1 lsb max guaranteed monotonic bipolar zero error 2 2 2 mv max at 25c; error at other temperatures obtained using bipolar zero tc bipolar zero temperature coefficient (tc) 1 2 2 2 ppm fsr/c max zero-scale error 2 2 2 mv max at 25c; error at other temperatures obtained using zero-scale tc zero-scale tc 1 2 2 2 ppm fsr/c max gain error 0.02 0.02 0.02 % fsr max at 25c; error at other temperatures obtained using gain tc gain tc 1 2 2 2 ppm fsr/c max dc crosstalk 1 0.5 0.5 0.5 lsb max reference input 1 reference input voltage 5 5 5 v nom 1% for specified performance dc input impedance 1 1 1 m min typically 100 m input current 10 10 10 a max typically 30 na reference range 1 to 7 1 to 7 1 to 7 v min to v max output characteristics 1 output voltage range 2 10.5263 10.5263 10.5263 v min to v max av dd /av ss = 11.4 v, v refin = 5 v 14 14 14 v min to v max av dd /av ss = 16.5 v, v refin = 7 v output voltage drift vs. time 13 13 13 ppm fsr/ 500 hours typ 15 15 15 ppm fsr/ 1000 hours typ short-circuit current 10 10 10 ma typ r iscc = 6 k, see figure 31 load current 1 1 1 ma max for specified performance capacitive load stability r load = 200 200 200 pf max r load = 10 k 1000 1000 1000 pf max dc output impedance 0.3 0.3 0.3 max digital inputs dv cc = 2.7 v to 5.25 v, jedec compliant input high voltage, v ih 2 2 2 v min input low voltage, v il 0.8 0.8 0.8 v max input current 1 1 1 a max per pin pin capacitance 10 10 10 pf max per pin
data sheet ad5764 rev. f | page 5 of 28 parameter a grade b grade c grade unit test conditions/comments digital outputs (d0, d1, sdo) 1 output low voltage 0.4 0.4 0.4 v max dv cc = 5 v 5%, sinking 200 a output high voltage dv cc ? 1 dv cc ? 1 dv cc ? 1 v min dv cc = 5 v 5%, sourcing 200 a output low voltage 0.4 0.4 0.4 v max dv cc = 2.7 v to 3.6 v, sinking 200 a output high voltage dv cc ? 0.5 dv cc ? 0.5 dv cc ? 0.5 v min dv cc = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 1 1 a max sdo only high impedance output capacitance 5 5 5 pf typ sdo only power requirements av dd /av ss 11.4 to 16.5 11.4 to 16.5 11.4 to 16.5 v min to v max dv cc 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 v min to v max power supply sensitivity 1 ?v out /?v dd ?85 ?85 ?85 db typ ai dd 3.5 3.5 3.5 ma/channel max outputs unloaded ai ss 2.75 2.75 2.75 ma/channel max outputs unloaded di cc 1.2 1.2 1.2 ma max v ih = dv cc , v il = dgnd, 750 a typical power dissipation 275 275 275 mw typ 12 v operation output unloaded 1 guaranteed by design and characterization; not production tested. 2 output amplifier headroom requirement is 1.4 v minimum. ac performance characteristics av dd = 11.4 v to 16.5 v, av ss = ?11.4 v to ?16.5 v, agndx = dgnd = refgnd = pgnd = 0 v; refab = refcd = 5 v; dv cc = 2.7 v to 5.25 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 3. parameter a grade b grade c grade unit test conditions/comments dynamic performance 1 output voltage settling time 8 8 8 s typ full-scale step to 1 lsb 10 10 10 s max 2 2 2 s typ 512 lsb step settling slew rate 5 5 5 v/s typ digital-to-analog glitch energy 8 8 8 nv-sec typ glitch impulse peak amplitude 25 25 25 mv max channel-to-channel isolation 80 80 80 db typ dac-to-dac crosstalk 8 8 8 nv-sec typ digital crosstalk 2 2 2 nv-sec typ digital feedthrough 2 2 2 nv-sec typ effect of input bus activity on dac outputs output noise (0.1 hz to 10 hz) 0.1 0.1 0.1 lsb p-p typ output noise (0.1 hz to 100 khz) 45 45 45 v rms max 1/f corner frequency 1 1 1 khz typ output noise spectral density 60 60 60 nv/hz typ measured at 10 khz complete system output noise spectral density 2 80 80 80 nv/hz typ measured at 10 khz 1 guaranteed by design and characterization; not production tested. 2 includes noise contributions from integrated reference buffers, 16-bit dac, and output amplifier.
ad5764 data sheet rev. f | page 6 of 28 timing characteristics av dd = 11.4 v to 16.5 v, av ss = ?11.4 v to ?16.5 v, agndx = dgnd = refgnd = pgnd = 0 v; refab = refcd = 5 v; dv cc = 2.7 v to 5.25 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 4. parameter 1 , 2 , 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 4 13 ns min 24 th sclk falling edge to sync rising edge t 6 90 ns min minimum sync high time t 7 2 ns min data setup time t 8 5 ns min data hold time t 9 1.7 s min sync rising edge to ldac falling edge (all dacs updated) 480 ns min sync rising edge to ldac falling edge (single dac updated) t 10 10 ns min ldac pulse width low t 11 500 ns max ldac falling edge to dac output response time t 12 10 s max dac output settling time t 13 10 ns min clr pulse width low t 14 2 s max clr pulse activation time t 15 5 , 6 25 ns max sclk rising edge to sdo valid t 16 13 ns min sync rising edge to sclk falling edge t 17 2 s max sync rising edge to dac output response time ( ldac = 0) t 18 170 ns min ldac falling edge to sync rising edge 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 2, figure 3, and figure 4. 4 standalone mode only. 5 measured with the load circuit of figure 5. 6 daisy-chain mode only.
data sheet ad5764 rev. f | page 7 of 28 timing diagrams 05303-002 db23 sclk sync sdin ldac ldac = 0 clr 12 24 db0 t 1 voutx voutx voutx t 4 t 6 t 3 t 2 t 5 t 8 t 7 t 10 t 9 t 10 t 11 t 12 t 12 t 17 t 18 t 13 t 14 figure 2. serial interface timing diagram ldac sdo sdin sync sclk 24 48 db23 db0 db23 db0 db23 input word for dac n undefined input word for dac n?1 input word for dac n db0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 15 t 16 t 5 t 10 t 9 05303-003 figure 3. daisy-chain timing diagram
ad5764 data sheet rev. f | page 8 of 28 05303-004 sdo sdin s yn c sclk 24 48 db23 db0 db23 db0 db23 undefined nop condition db0 input word specifies register to be read selected register data clocked out figure 4. readback timing diagram 200a i ol 200a i oh v oh (min) or v ol (max) t o sdo pin c l 50pf 05303-005 figure 5. load circuit for sdo timing diagram
data sheet ad5764 rev. f | page 9 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 5. parameter rating av dd to agndx, dgnd ?0.3 v to +17 v av ss to agndx, dgnd +0.3 v to ?17 v dv cc to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to dv cc + 0.3 v or 7 v (whichever is less) digital outputs to dgnd ?0.3 v to dv cc + 0.3 v refab, refcd to agndx, pgnd ?0.3 v to av dd + 0.3 v vouta, voutb, voutc, voutd to agndx av ss to av dd agndx to dgnd ?0.3 v to +0.3 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c 32-lead tqfp ja thermal impedance 65c/w jc thermal impedance 12c/w lead temperature jedec industry standard soldering j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5764 data sheet rev. f | page 10 of 28 pin configuration and fu nction descriptions nc = no connect sync sclk sdin sdo clr ldac d1 d0 agnda vouta voutb agndb agndc voutc voutd agndd rstout rstin dgnd dv cc av dd pgnd iscc av ss bin/2scomp av dd av ss nc refgnd nc refcd refab 1 2 3 4 5 6 7 8 23 22 21 18 19 20 24 17 pin 1 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad5764 top view (not to scale) 05303-006 figure 6. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 sync active low input. this is the frame synchronization signal for the serial interface. while sync is low, data is transferred in on the falling edge of sclk. 2 sclk serial clock input. data is clocke d into the input shift register on the falling edge of sclk. this operates at clock speeds up to 30 mhz. 3 sdin serial data input. data must be valid on the falling edge of sclk. 4 sdo serial data output. used to clock data from the serial register in daisy-chain or readback mode. 5 clr negative edge triggered input. asserting this pin se ts the data register to 0x0000. there is an internal pull-up device on this logic input. therefore, this pin can be left floating and defaults to a logic 1 condition. 6 ldac load dac. logic input. this is used to update th e data register and conseq uently the analog outputs. when tied permanently low, the addressed data register is updated on the rising edge of sync . if ldac is held high during the write cycle, the da c input shift register is updated but the output update is held off until the falling edge of ldac . in this mode, all analog outputs can be updated simultaneously on the falling edge of ldac . the ldac pin must not be left unconnected. 7, 8 d0, d1 digital i/o port. the user can set up these pins as in puts or outputs that are configurable and readable over the serial interface. when configured as inputs, these pins have weak internal pull-ups to dv cc . when programmed as outputs, d0 and d1 are referenced by dv cc and dgnd. 9 rstout reset logic output. this is the output from the on-c hip voltage monitor used in the reset circuit. if desired, it can be used to control other system components. 10 rstin reset logic input. this input allo ws external access to the internal reset logic. applying a logic 0 to this input clamps the dac output s to 0 v. in normal operation, rstin should be tied to logic 1. register values remain unchanged. 11 dgnd digital ground. 12 dv cc digital supply. voltage ranges from 2.7 v to 5.25 v. 13, 31 av dd positive analog supply. voltage ranges from 11.4 v to 16.5 v. 14 pgnd ground reference point for analog circuitry. 15, 30 av ss negative analog supply. voltage ranges from ?11.4 v to ?16.5 v. 16 iscc resistor connection for pin programmable short-circuit current. this pin is used in association with an optional external resistor to agnd to program the short-circuit current of the output amplifiers. refer to the design features section for further details. 17 agndd ground reference pin for dac d output amplifier. 18 voutd analog output voltage of dac d. this pin is a bu ffered output with a nominal full-scale output range of 10 v. the output amplifier is capable of directly driving a 10 k, 200 pf load. 19 voutc analog output voltage of dac c. this pin is a bu ffered output with a nominal full-scale output range of 10 v. the output amplifier is capable of directly driving a 10 k, 200 pf load. 20 agndc ground reference pin for dac c output amplifier.
data sheet ad5764 rev. f | page 11 of 28 pin no. mnemonic description 21 agndb ground reference pin for dac b output amplifier. 22 voutb analog output voltage of dac b. buffered output w i th a nominal full-scale output range of 10 v. the output amplifier is capable of directly driving a 10 k, 200 pf load. 23 vouta ale output range of 10 v. analog output voltage of dac a. buffered output wi th a nominal full-sc the output amplifier is capable of directly driving a 10 k, 200 pf load. 24 agnda ground reference pin for dac a output amplifier. 25 refab external reference voltage input for channel a and channel b. reference input range is 1 v to 7 v; programs the full-scale output voltage. v refin = 5 v for specified performance. 26 refcd t range is 1 v to 7 v; external reference voltage input for channel c and channel d. reference inpu programs the full-scale output voltage. v refin = 5 v for specified performance. 27, 29 nc no connect. 28 refgnd eturn for the reference generator and buffers. reference ground r 32 bin/ 2sco mp dv cc or dgnd. when hardwired to determines the dac coding. this pin should be hardwired to either dv cc , input coding is offset binary. when hardwire d to dgnd, input coding is twos complement (see table 7 and table 8 ).
ad5764 data sheet rev. f | page 12 of 28 typical performance characteristics 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 10000 20000 30000 40000 50000 60000 inl error (lsb) dac code 05303-007 t a = 25c av dd /av ss = 15v v refin = 5v figure 7. integral nonlinearity error vs. code, av dd /av ss = 15 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 10000 20000 30000 40000 50000 60000 inl error (lsb) dac code 05303-008 t a = 25c av dd /av ss = 12v v refin = 5v figure 8. integral nonlinearity error vs. code, av dd /av ss = 12 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 10000 20000 30000 40000 50000 60000 dnl error (lsb) dac code 05303-011 t a = 25c av dd /av ss = 15v v refin = 5v figure 9. differential nonlinearity error vs. code, av dd /av ss = 15 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 10000 20000 30000 40000 50000 60000 dnl error (lsb) dac code 05303-012 t a = 25c av dd /av ss = 12v v refin = 5v figure 10. differential nonlinearity error vs. code, av dd /av ss = 12 v 0.5 0.4 0.3 0.2 0.1 ?0.2 ?0.1 0 ?40 100 ?20 0 20 40 60 80 inl error (lsb) temperature (c) 05303-015 t a = 25c av dd /av ss = 15v v refin = 5v figure 11. integral nonlinearity error vs. temperature, av dd /av ss = 15 v 0.5 0.4 0.3 0.2 0.1 ?0.1 0 ?40 100 ?20 0 20 40 60 80 inl error (lsb) temperature (c) 05303-016 t a = 25c av dd /av ss = 12v v refin = 5v figure 12. integral nonlinearity error vs. temperature, av dd /av ss = 12 v
data sheet ad5764 rev. f | page 13 of 28 0.15 0.10 0.05 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 ?40 100 ?20 0 20 40 60 80 dnl error (lsb) temperature (c) 05303-019 t a = 25c av dd /av ss = 15v v refin = 5v figure 13. differential nonlinearity error vs. temperature, av dd /av ss = 15 v 0.15 0.10 0.05 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 ?40 100 ?20 0 20 40 60 80 dnl error (lsb) temperature (c) 05303-020 t a = 25c av dd /av ss = 12v v refin = 5v figure 14. differential nonlinearity error vs. temperature, av dd /av ss = 12 v 0.5 0.4 0.3 0.2 0.1 0 ?0.2 ?0.1 11.4 16.4 15.4 14.4 13.4 12.4 inl error (lsb) supply voltage (v) 05303-023 t a = 25c v refin = 5v figure 15. integral nonlinearity error vs. supply voltage 0.15 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 11.4 16.4 15.4 14.4 13.4 12.4 dnl error (lsb) supply voltage (v) 05303-025 t a = 25c v refin = 5v figure 16. differential nonlinearity error vs. supply voltage 0.8 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 17 56 4 3 2 inl error (lsb) reference voltage (v) 05303-027 t a = 25c av dd /av ss = 16.5v figure 17. integral nonlinearity error vs. reference voltage, av dd /av ss = 16.5 v 0.4 0.3 0.2 0.1 ?0.4 ?0.3 ?0.2 ?0.1 0 17 56 4 3 2 dnl error (lsb) reference voltage (v) 05303-031 t a = 25c av dd /av ss = 16.5v figure 18. differential nonlinearity error vs. reference voltage, av dd /av ss = 16.5 v
ad5764 data sheet rev. f | page 14 of 28 0.6 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 17 56 4 3 2 tue (mv) reference voltage (v) 05303-035 t a = 25c av dd /av ss = 16.5v figure 19. total unadjusted error vs. reference voltage, av dd /av ss = 16.5 v 14 13 12 11 10 9 8 11.4 16.4 15.4 14.4 13.4 12.4 i dd /i ss (ma) av dd /av ss (v) 05303-037 t a = 25c v refin = 5v |i ss | |i dd | figure 20. i dd /i ss vs. av dd /av ss 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 ?40 100 80 60 40 20 0 ?20 zero-scale error (mv) temperature (c) 05303-038 v refin = 5v av dd /av ss = 15v av dd /av ss = 12v figure 21. zero-scale error vs. temperature 0.8 0.6 0.4 ?0.4 ?0.2 0 0.2 ?40 100 80 60 40 20 0 ?20 bipolar zero error (mv) temperature (c) 05303-039 v refin = 5v av dd /av ss = 15v av dd /av ss = 12v figure 22. bipolar zero error vs. temperature 1.4 0.6 0.8 1.0 1.2 0.4 ?0.2 0 0.2 ?40 100 80 60 40 20 0 ?20 gain error (mv) temperature (c) 05303-040 v refin = 5v av dd /av ss = 15v av dd /av ss = 12v figure 23. gain error vs. temperature 0.0014 0.0013 0.0012 0.0011 0.0010 0.0009 0.0008 0.0007 0.0006 05 4.54.03.53.02.52.01.5 1.00.5 di cc (ma) v logic 05303-041 . 0 t a = 25c 5v 3v figure 24. di cc vs. logic input voltage
data sheet ad5764 rev. f | page 15 of 28 7000 3000 4000 5000 6000 2000 ?1000 0 1000 ?10 10 5 0 ?5 output voltage delta (v) source/sink current (ma) 05303-042 av dd /av ss = 15v av dd /av ss = 12v t a = 25c v refin = 5v ri scc = 6k ? figure 25. source and sink capability of output amplifier with positive full scale loaded 10000 7000 8000 9000 3000 4000 5000 6000 2000 ?1000 0 1000 ?12 8 3 ?2 ?7 output voltage delta (v) source/sink current (ma) 05303-043 15v supplies 12v supplies t a = 25c v refin = 5v ri scc = 6k ? figure 26. source and sink capability of output amplifier with negative full scale loaded 05303-044 ch1 3.00v m1.00s ch1 ?120mv 1 av dd /av ss = 15v t a = 25c v refin = 5v 1s/div figure 27. full-scale settling time ? 4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 ?20 ?22 ?24 ?26 ?2.0?1.5?1.0?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v out (mv) time (s) 05303-047 av dd /av ss = 12v v refin = 5v t a = 25c 0x8000 to 0x7fff 500ns/div figure 28. major code transition glitch energy, av dd /av ss = 12 v
ad5764 data sheet rev. f | page 16 of 28 05303-048 ch4 50.0v m1.00s ch4 26v 4 av dd /av ss = 15v midscale loaded v refin = 0v 50v/div 10 9 8 7 6 5 4 3 2 1 0 01 100 80 60 40 20 short-circuit current (ma) ri scc (k ? ) 05303-050 2 0 av dd /av ss = 15v t a = 25c v refin = 5v figure 31. short-circuit current vs. ri scc figure 29. peak-to-peak noise (100 khz bandwidth) 05303-055 ch1 10.0v b w ch3 10.0mv b w t 29.60% ch2 10.0v m100s a ch1 7.80mv 1 2 3 av dd /av ss = 12v v refin = 5v t a = 25c ramp time = 100s load = 200pf||10k ? t figure 30. v out vs. av dd /av ss on power-up
data sheet ad5764 rev. f | page 17 of 28 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 7 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic. a typical dnl vs. code plot can be seen in figure 9 . monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5764 is monotonic over its full operating temperature range. bipolar zero error bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 v when the data register is loaded with 0x8000 (offset binary coding) or 0x0000 (twos complement coding). a plot of bipolar zero error vs. temperature can be seen in figure 22 . bipolar zero temperature coefficient (tc) bipolar zero tc is the measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. full-scale error full-scale error is a measure of the output error when full-scale code is loaded to the data register. ideally, the output voltage should be 2 v ref ? 1 lsb. full-scale error is expressed in percentage of full-scale range. negative full-scale error/zero-scale error negative full-scale error is the error in the dac output voltage when 0x0000 (offset binary coding) or 0x8000 (twos complement coding) is loaded to the data register. ideally, the output voltage should be ?2 v ref . a plot of zero-scale error vs. temperature can be seen in figure 21 . output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed of a voltage-output dac is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. a plot of gain error vs. temperature can be seen in figure 23 . tot a l un a dju s te d e r ror total unadjusted error (tue) is a measure of the output error considering all the various errors. a plot of total unadjusted error vs. reference voltage can be seen in figure 19 . zero-scale error temperature coefficient (tc) zero-scale error tc is a measure of the change in zero-scale error with a change in temperature. zero-scale error tc is expressed in ppm fsr/c. gain error temperature coefficient (tc) gain error tc is a measure of the change in gain error with changes in temperature. gain error tc is expressed in ppm fsr/c. digital-to-analog glitch energy digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the data register changes state. it is normally specified as the area of the glitch in nv-sec, and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000); see figure 28 . digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is speci- fied in nv-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. power supply sensitivity power supply sensitivity indicates how the output of the dac is affected by changes in the power supply voltage. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac, and is expressed in lsbs. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-sec. channel-to-channel isolation channel-to-channel isolation is the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in db. digital crosstalk digital crosstalk is a measure of the impulse injected into the analog output of one dac from the digital inputs of another dac, but is measured when the dac output is not updated. it is specified in nv-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa.
ad5764 data sheet rev. f | page 18 of 28 theory of operation the ad5764 is a quad, 16-bit, serial input, bipolar voltage output dac and operates from supply voltages of 11.4 v to 16.5 v and has a buffered output voltage of up to 10.5263 v. data is written to the ad5764 in a 24-bit word format, via a 3-wire serial interface. the device also offers an sdo pin that is available for daisy- chaining or readback. the ad5764 incorporates a power-on reset circuit, which ensures that the data register powers up loaded with 0x0000. the ad5764 features a digital i/o port that can be programmed via the serial interface, on-chip reference buffers and per channel digital gain, and offset registers. dac architecture the dac architecture of the ad5764 consists of a 16-bit, current mode, segmented r-2r dac. the simplified circuit diagram for the dac section is shown in figure 32 . the four msbs of the 16-bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of the 15 matched resistors to either agndx or iout. the remain- ing 12 bits of the data-word drive switch s0 to switch s11 of the 12-bit r-2r ladder network. 05303-060 2r e15 v ref 2r e14 e1 2r s11 rr r 2r s10 2r 12-bit, r-2r ladder 4 msbs decoded into 15 equal segments voutx 2r s0 2r agndx r/8 iout figure 32. dac ladder structure reference buffers the ad5764 operates with an external reference. the reference inputs (refab and refcd) have an input range up to 7 v. this input voltage is used to provide a buffered positive and negative reference for the dac cores. the positive reference is given by +v ref = 2 v ref the negative reference to the dac cores is given by ?v ref = ?2 v ref these positive and negative reference voltages (along with the gain register values) define the output ranges of the dacs. serial interface the ad5764 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 mhz and is compatible with spi, qspi?, microwire?, and dsp standards. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24-bit word under the control of a serial clock input, sclk. the input shift register consists of a read/ write bit, three register select bits, three dac address bits, and 16 data bits, as shown in table 9 . the timing diagram for this operation is shown in figure 2 . upon power-up, the data register is loaded with zero code (0x0000), and the outputs are clamped to 0 v via a low imped- ance path. the outputs can be updated with the zero code value at this time by asserting either ldac or clr . the corresponding output voltage depends on the state of the bin/ 2scomp pin. if the bin/ 2scomp pin is tied to dgnd, the data coding is twos complement, and the outputs update to 0 v. if the bin/ 2scomp pin is tied to dv cc , the data coding is offset binary, and the outputs update to negative full scale. to power up the outputs with zero code loaded to the outputs, hold the clr pin low during power-up. standalone operation the serial interface works with both a continuous and noncon- tinuous serial clock. a continuous sclk source can only be used if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used and sync must be taken high after the final clock to latch the data. the first falling edge of sync starts the write cycle. exactly 24 falling clock edges must be applied to sclk before sync is brought high again. if sync is brought high before the 24 th falling sclk edge, the data written is invalid. if more than 24 falling sclk edges are applied before sync is brought high, the input data is also invalid. the input shift register addressed is updated on the rising edge of sync . for another serial transfer to take place, sync must be brought low again. after the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. when the data has been transferred into the chosen register of the addressed dac, the data register and outputs can be updated by taking ldac low.
data sheet ad5764 rev. f | page 19 of 28 daisy-chain operation 05303-061 68hc11 1 miso sync sdin sclk mosi sck pc7 pc6 ldac sdo sync sclk ldac sdo sync sclk ldac sdo sdin sdin 1 additional pins omitted for clarity ad5764 1 ad5764 1 ad5764 1 figure 33. daisy-chaining the ad5764 for systems that contain several devices, the sdo pin can be used to daisy-chain several devices together. this daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. the first falling edge of sync starts the write cycle. the sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connect- ing the sdo of the first device to the sdin input of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24n, where n is the total number of ad5764 devices in the chain. when the serial transfer to all devices is complete, sync is taken high. this latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. the serial clock can be a continuous or a gated clock. a continuous sclk source can only be used if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. readback operation be fore a readback operation is initiated, the sdo pin must be enabled by writing to the function register and clearing the sdo disable bit; this bit is cleared by default. readback mode is invoked by setting the r/ w bit = 1 in the serial input shift register write. with r/ w = 1, bit a2 to bit a0, in association with bit reg2, bit reg1, and bit reg0, select the register to be read. the remaining data bits in the write sequence are dont cares. during the next spi write, the data appearing on the sdo output contain the data from the previously addressed register. for a read of a single register, the nop command can be used in clocking out the data from the selected register on sdo. the readback diagram in shows the readback sequence. for example, to read back the fine gain register of channel a on the ad5764, implement the following: figure 4 1. write 0xa0xxxx to the ad5764 input shift register. this configures the ad5764 for read mode with the fine gain register of channel a selected. note that all the data bits, db15 to db0, are dont cares. 2. follow this with a second write, an nop condition, 0x00xxxx. during this write, the data from the fine gain register is clocked out on the sdo line, that is, data clocked out contain the data from the fine gain register in bit db5 to bit db0. simultaneous updating via ldac depending on the status of both sync and ldac , and after data has been transferred into the input register of the dacs, there are two ways in which the data register and dac outputs can be updated. individual dac updating in this mode, ldac is held low while data is being clocked into the input shift register. the addressed dac output is updated on the rising edge of sync . simultaneous updating of all dacs in this mode, ldac is held high while data is being clocked into the input shift register. all dac outputs are updated by taking ldac low any time after sync has been taken high. the update now occurs on the falling edge of ldac . v out x data register interface logic output i/v amplifier ldac sdo sdin 16-bit dac v refin sync input register sclk 05303-062 figure 34. simplified serial interface of input loading circuitry for one dac channel
ad5764 data sheet rev. f | page 20 of 28 the output voltage expression for the ad5764 is given by transfer function ? ? ? ? ? ? +?= 536,65 4 2 d v v v refin refin out table 7 and table 8 show the ideal input code to output voltage relationship for the ad5764 for both offset binary and twos complement data coding, respectively. where: d is the decimal equivalent of the code loaded to the dac. v refin is the reference voltage applied at the refab/refcd pins. table 7. ideal output voltage to input code relationship offset binary data coding digital input analog output asynchronous clear ( clr ) msb lsb voutx 1111 1111 1111 1111 +2 v ref (32,767/32,768) clr is a negative edge triggered clear that allows the outputs to be cleared to either 0 v (twos complement coding) or negative full scale (offset binary coding). it is necessary to maintain clr low for a minimum amount of time (see ) for the operation to complete. when the figure 2 clr signal is returned high, the output remains at the cleared value until a new value is programmed. if at power-on, clr is at 0 v, then all dac outputs are updated with the clear value. a clear can also be initiated through software by writing command 0x04xxxx to the ad5764. 1000 0000 0000 0001 +2 v ref (1/32,768) 1000 0000 0000 0000 0 v 0111 1111 1111 1111 ?2 v ref (1/32,768) 0000 0000 0000 0000 ?2 v ref (32,767/32,768) table 8. ideal output voltage to input code relationship twos complement data coding digital input analog output msb lsb voutx 0111 1111 1111 1111 +2 v ref (32,767/32,768) 0000 0000 0000 0001 +2 v ref (1/32,768) 0000 0000 0000 0000 0 v 1111 1111 1111 1111 ?2 v ref (1/32,768) 1000 0000 0000 0000 ?2 v ref (32,767/32,768) table 9. input shift register bit map msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db15:db0 r/ w 0 reg2 reg1 reg0 a2 a1 a0 data table 10. input shift register bit functions bit description r/ w indicates a read from or a write to the addressed register. reg2, reg1, reg0 used in association with the address bits to determine if a read or write operation is to the data register, offset register, coarse gain register, fine gain register, or function register. reg2 reg1 reg0 function 0 0 0 function register 0 1 0 data register 0 1 1 coarse gain register 1 0 0 fine gain register 1 0 1 offset register a2, a1, a0 these bits are used to decode the dac channels. a2 a1 a0 channel address 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 0 0 all dacs data data bits.
data sheet ad5764 rev. f | page 21 of 28 function register the function register is addressed by setting the three reg bits to 000. the values written to the address bits and the data bi ts determine the function addressed. the functions available via the function register are outlined in table 11 and table 12 . table 11. function register options reg2 reg1 reg0 a2 a1 a0 db15:db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 nop, data = dont care 0 0 0 0 0 1 dont care local ground offset adjust d1 direction d1 value d0 direction d0 value sdo disable 0 0 0 1 0 0 clear, data = dont care 0 0 0 1 0 1 load, data = dont care table 12. explanation of function register options option description nop no operation instruction used in readback operations. local ground offset adjust set by the user to enable the local ground offset adju st function. cleared by the user to disable the local ground offset adjust functi on (default). refer to the design features section for further details. d0/d1 direction set by the user to enable d0/d1 as outputs. cleared by the user to enab le d0/d1 as inputs (default). refer to the design features section for further details. d0/d1 value i/o port status bits. logic values written to these lo cations determine the logic outputs on the d0 and d1 pins when configured as outputs. thes e bits indicate the status of the d0 and d1 pins when the i/o port is active as an input. when enabled as inputs, th ese bits are dont cares during a write operation. sdo disable set by the user to disabl e the sdo output. cleared by the user to enable the sdo output (default). clear addressing this function resets the dac outputs to 0 v in twos complement mode and negative full scale in binary mode. load addressing this function updates the data register and consequently the analog outputs. data register the data register is addressed by setting the three reg bits to 010. the dac address bits select with which dac channel the dat a transfer is to take place (see tabl e 10 ). the data bits are in position db15 to position db0, as shown in table 13 . table 13. programming the data register bit map reg2 reg1 reg0 a2 a1 a0 db15:db0 0 1 0 dac address 16-bit dac data coarse gain register the coarse gain register is addressed by setting the three reg bits to 011. the dac address bits select with which dac channel the data transfer is to take place (see tabl e 10 ). the coarse gain register is a 2-bit register and allows the user to select the output range of each dac, as shown in table 14 and table 15 . table 14. programming the coarse gain register bit map reg2 reg1 reg0 a2 a1 a0 db15: db2 db1 db0 0 1 1 dac address dont care cg1 cg0 table 15. output range selection output range cg1 cg0 10 v (default) 0 0 10.2564 v 0 1 10.5263 v 1 0
ad5764 data sheet rev. f | page 22 of 28 fine gain register the fine gain register is addressed by setting the three reg bits to 100. the dac address bits select with which dac channel the data transfer is to take place (see table 10 ). the fine gain register is a 6-bit register and allows the user to adjust the gain of each dac channel by ?32 lsbs to +31 lsbs in 1 lsb increments, as shown in table 1 6 and table 17 . the adjustment is made to both the positive full-scale points and the negative full-scale points simultaneously, each point being adjusted by ? of one step. the fine gain register coding is twos complement. offset register the offset register is addressed by setting the three reg bits to 101. the dac address bits select with which dac channel the data transfer is to take place (see table 10 ). the ad5764 offset register is an 8-bit register and allows the user to adjust the offset of each channel by ?16 lsbs to +15.875 lsbs in increments of ? lsb, as shown in table 18 and table 19 . the offset register coding is twos complement. table 16. programming the fi ne gain register bit map reg2 reg1 reg0 a2 a1 a0 db15:db6 db5 db4 db3 db2 db1 db0 1 0 0 dac address dont care fg5 fg4 fg3 fg2 fg1 fg0 table 17. fine gain register options gain adjustment fg5 fg4 fg3 fg2 fg1 fg0 +31 lsbs 0 1 1 1 1 1 +30 lsbs 0 1 1 1 1 0 +2 lsbs 0 0 0 0 1 0 +1 lsb 0 0 0 0 0 1 no adjustment (default) 0 0 0 0 0 0 ?1 lsb 1 1 1 1 1 1 ?2 lsbs 1 1 1 1 1 0 ?31 lsbs 1 0 0 0 0 1 ?32 lsbs 1 0 0 0 0 0 table 18. programming the offset register bit map reg2 reg1 reg0 a2 a1 a0 db15:db8 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 dac address dont care of7 of6 of5 of4 of3 of2 of1 of0 table 19. ad5764 offset register options offset adjustment of7 of6 of5 of4 of3 of2 of1 of0 +15.875 lsbs 0 1 1 1 1 1 1 1 +15.75 lsbs 0 1 1 1 1 1 1 0 +0.25 lsbs 0 0 0 0 0 0 1 0 +0.125 lsbs 0 0 0 0 0 0 0 1 no adjustment (default) 0 0 0 0 0 0 0 0 ?0.125 lsbs 1 1 1 1 1 1 1 1 ?0.25 lsbs 1 1 1 1 1 1 1 0 ?15.875 lsbs 1 0 0 0 0 0 0 1 ?16 lsbs 1 0 0 0 0 0 0 0
data sheet ad5764 rev. f | page 23 of 28 offset and gain adjustment worked example using the information provided in the fine gain register and offset register sections, the following worked example demon- strates how the ad5764 functions can be used to eliminate both offset and gain errors. because the ad5764 is factory calibrated, offset and gain errors should be negligible. however, errors can be introduced by the system that the ad5764 is operating within; for example, a voltage reference value that is not equal to 5 v introduces a gain error. an output range of 10 v and twos complement data coding is assumed. removing offset error the ad5764 can eliminate an offset error in the range of ?4.88 mv to +4.84 mv with a step size of ? of a 16-bit lsb. calculate the step size of the offset adjustment. v14.38 82 20 16 = = sizestepadjust offset measure the offset error by programming 0x0000 to the data register and measuring the resulting output voltage. for this example, the measured value is 614 v. calculate the number of offset adjustment steps that this value represents. steps16 v14.38 v614 = = = sizestepoffset valu e offse t measure d stepsofnumber the offset error measured is positive, therefore, a negative adjustment of 16 steps is required. the offset register is eight bits wide and the coding is twos complement. the required offset register value can be calculated as follows: convert the adjustment value to binary: 00010000. convert this to a negative twos complement number by inverting all bits and adding 1 to obtain 11110000, the value that should be programmed to the offset register. note that this twos complement conversion is not necessary in the case of a positive offset adjustment. the value to be programmed to the offset register is simply the binary representation of the adjustment value. removing gain error the ad5764 can eliminate a gain error at negative full-scale output in the range of ?9.77 mv to +9.46 mv with a step size of ? of a 16-bit lsb. calculate the step size of the gain adjustment. v59.152 22 20 16 = = sizestepadjustgain measure the gain error by programming 0x8000 to the data register and measuring the resulting output voltage. the gain error is the difference between this value and ?10 v. for this example, the gain error is ?1.2 mv. calculate how many gain adjustment steps this value represents. steps8 v59.152 mv2.1 = = = sizestepgain valuegain measured stepsofnumber the gain error measured is nega tive (in terms of magnitude); therefore, a positive adjustment of eight steps is required. the gain register is 6 bits wide and the coding is twos complement, the required gain register value can be determined as follows: convert the adjustment value to binary: 001000. the value to be programmed to the gain register is simply this binary number.
ad5764 data sheet rev. f | page 24 of 28 design features analog output control in many industrial process control applications, it is vital that the output voltage be controlled during power-up and during brownout conditions. when the supply voltages are changing, the voutx pins are clamped to 0 v via a low impedance path. to prevent the output amp being shorted to 0 v during this time, transmission gate g1 is also opened (see figure 35 ). these condi- tions are maintained until the power supplies stabilize and a valid word is written to the data register. at this time, g2 opens and g1 closes. both transmission gates are also externally controllable via the reset logic ( rstin ) control input. for instance, if rstin is driven from a battery supervisor chip, the rstin input is driven low to open g1 and close g2 upon power-down or during a brownout. conversely, the on-chip voltage detector output ( rstout ) is also available to the user to control other parts of the system. the basic transmission gate functionality is shown in . figure 35 05303-063 g1 g2 rstout rstin vouta agnda voltage monitor and control figure 35. analog output control circuitry digital offset and gain control the ad5764 incorporates a digital offset adjust function with a 16 lsb adjust range and 0.125 lsb resolution. the coarse gain register allows the user to adjust the ad5764 full-scale output range. the full-scale output can be programmed to achieve full- scale ranges of 10 v, 10.2564 v, and 10.5263 v. a fine gain trim is also provided. programmable short-circuit protection the short-circuit current of the output amplifiers can be pro- grammed by inserting an external resistor between the iscc pin and pgnd. the programmable range for the current is 500 a to 10 ma, corresponding to a resistor range of 120 k to 6 k. the resistor value is calculated as follows: c i r s 60 = if the iscc pin is left unconnected, the short-circuit current limit defaults to 5 ma. note that limiting the short-circuit current to a small value can affect the slew rate of the output when driving into a capacitive load; therefore, the value of the programmed short circuit should take into account the size of the capacitive load being driven. digital i/o port the ad5764 contains a 2-bit digital i/o port (d1 and d0). these bits can be configured as inputs or outputs independently, and can be driven or have their values read back via the serial interface. the i/o port signals are referenced to dv cc and dgnd. when configured as outputs, they can be used as control signals to multiplexers or can be used to control calibration circuitry elsewhere in the system. when configured as inputs, the logic signals from limit switches can, for example, be applied to d0 and d1 and can be read back via the digital interface. local ground offset adjust the ad5764 incorporates a local ground offset adjust feature that, when enabled in the function register, adjusts the dac outputs for voltage differences between the individual dac ground pins, agndx, and the refgnd pin, ensuring that the dac output voltages are always with respect to the local dac ground pin. for instance, if pin agnda is at +5 mv with respect to the refgnd pin and vouta is measured with respect to agnda, a ?5 mv error results, enabling the local ground offset adjust feature to adjust vouta by +5 mv, eliminating the error.
data sheet ad5764 rev. f | page 25 of 28 applications information typical operating circuit figure 36 shows the typical operating circuit for the ad5764. the only external components needed for this precision 16-bit dac are a reference voltage source, decoupling capacitors on the supply pins and reference inputs, and an optional short- circuit current setting resistor. because the device incorporates reference buffers, it eliminates the need for an external bipolar reference and associated buffers. this leads to an overall savings in both cost and board space. in figure 36 , av dd is connected to +15 v and av ss is connected to ?15 v. however, av dd can operate with supplies from +11.4 v to +16.5 v and av ss can operate with supplies from ?11.4 v to ?16.5 v. 1 2 3 4 5 6 7 8 23 22 21 18 19 20 24 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad5764 sync sclk sdin sdo d0 ldac clr d1 vouta voutb agndb voutd voutc agndc agnda agndd rstout rstin dgnd dv cc av dd pgnd av ss iscc bin/2scomp av dd av ss nc refgnd nc refcd refab sync sclk sdin sdo ldac d0 d1 rstout rstin bin/2scomp +5v +5v +15v ?15v nc = no connect +15v ?15v vouta voutb voutc voutd 100nf 100nf 100nf 10f 100nf 100nf 100nf 10f 10f 10f 10f 05303-064 adr02 4 gnd 2 6 vout vin +15 v figure 36. typical operating circuit
ad5764 data sheet rev. f | page 26 of 28 precision voltage reference selection to achieve the optimum performance from the ad5764 over its full operating temperature range, a precision voltage reference must be used. consideration should be given to the selection of a precision voltage reference. the ad5764 has two reference inputs, refab and refcd. the voltages applied to the refer- ence inputs are used to provide a buffered positive and negative reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the device. there are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long-term drift, and output voltage noise. initial accuracy error on the output voltage of an external refer- ence can lead to a full-scale error in the dac. therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. choosing a reference with an output trim adjustment, such as the adr425 , allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. the trim adjust- ment can also be used at temperature to trim out any error. long-term drift is a measure of how much the reference output voltage drifts over time. a reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. the temperature coefficient of a reference output voltage affects inl, dnl, and tue. choose a reference with a tight temperature coefficient specification to reduce the dependence of the dac output voltage on ambient conditions. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. choosing a reference with as low an output noise voltage as practical for the system resolution required is important. precision voltage references such as the adr435 (xfet? design) produce low output noise in the 0.1 hz to 10 hz region. however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. table 20. some precision references recommended for use with the ad5764 part no. initial accuracy (mv max) long-term drift (ppm typ) temp drift (ppm/c max) 0.1 hz to 10 hz noise (v p-p typ) adr435 2 40 3 8 adr425 2 50 3 3.4 adr02 5 50 3 10 adr395 5 50 9 8
data sheet ad5764 rev. f | page 27 of 28 layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the pcb on which the ad5764 is mounted must be designed so that the anal og and digital sections are sepa- rated and confined to certain areas of the board. if the ad5764 is in a system where multiple devices require an agnd-to-dgnd connection, the connection is to be made at one point only. the star ground point is established as close as possible to the device. the ad5764 must have ample supply bypassing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor must have low effective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5764 must be as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line . fast switching signals, such as clocks, must be shielded with digital ground to avoid radiating noise to other parts of the board, and must never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce crosstalk between them (not required on a multilayer board, which has a separate ground plane; however, it is helpful to separate the lines). it is essential to minimize noise on the reference inputs because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the board must ru n at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is recommended, but not always possible with a double- sided board. in this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the solder side. galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. isocoup- lers provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5764 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 37 shows a 4-channel isolated interface to the ad5764 using an adum1400 . for more information, go to www.analog.com . 05303-065 v ia serial clock out to sclk v oa encode decode v ib serial data out to sdin v ob encode decode v ic sync out v oc encode decode v id control out v od encode decode microcontroller adum1400* *additional pins omitted for clarity. to sync to ldac figure 37. isolated interface microprocessor interfacing microprocessor interfacing to the ad5764 is via a serial bus that uses a standard protocol that is compatible with micro- controllers and dsp processors. the communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5764 requires a 24-bit data-word with data valid on the falling edge of sclk. for all the interfaces, the dac output update can be performed automatically when all the data is clocked in, or it can be done under the control of ldac . the contents of the data register can be read using the readback function. evaluation board the ad5764 comes with a full evaluation board to aid designers in evaluating the high performance of the part with minimum effort. all that is required with the evaluation board is a power supply and a pc. the ad5764 evaluation kit includes a populated, tested ad5764 pcb. the evaluation board interfaces to the usb port of the pc. software is available with the evaluation board, which allows the user to easily program the ad5764. the software runs on any pc that has microsoft? windows? 2000/nt/xp installed. the eval-ad5764eb data sheet is available, which gives full details on the operation of the evaluation board.
ad5764 data sheet rev. f | page 28 of 28 outline dimensions compliant to jedec standards ms-026-ab a 0.45 0.37 0.30 0.80 bsc lead pitch 7.00 bsc sq 9.00 bsc sq 1 24 25 32 8 9 17 16 1.20 max 0.75 0.60 0.45 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity seating plane 0 min 7 3.5 0 0.15 0.05 view a rotated 90 ccw view a pin 1 top view (pins down) 020607-a figure 38. 32-lead thin plastic quad flat package [tqfp] (su-32-2) dimensions shown in millimeters ordering guide model 1 inl temperature range package description package option ad5764asuz 4 lsb max ?40c to +85c 32-lead tqfp su-32-2 ad5764asuz-reel7 4 lsb max ?40c to +85c 32-lead tqfp su-32-2 ad5764bsuz 2 lsb max ?40c to +85c 32-lead tqfp su-32-2 ad5764bsuz-reel7 2 lsb max ?40c to +85c 32-lead tqfp su-32-2 ad5764csuz 1 lsb max ?40c to +85c 32-lead tqfp su-32-2 ad5764csuz-reel7 1 lsb max ?40c to +85c 32-lead tqfp su-32-2 EVAL-AD5764EBZ evaluation board 1 z = rohs compliant part. ?2006C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05303-0-9/11(f)

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